Design of FPGA Programmable Logic System
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Authors

Kevin Gautama is a systems design and programming engineer with 16 years of expertise in the fields of electrical and electronics and information technology.

He teaches at the Hanoi University of Industry in the period 2003-2011 and he has a certificate of vocational training by the Ministry of Industry and Commerce and the Hanoi University of Industry.

From extensive design experience through numerous engineering projects, the author founded the Enziin Academy.

The Enziin Academy is a startup in the field of educational, it's core goal is to training design engineers in the fields technology related.

The Enziin Academy is headquartered in Stockholm-Sweden with an orientation operating multi-lingual and global.

The author's skills in IT:

  • Implementing the application infrastructure on Amazon's cloud computing platform.
  • Linux server system administration (Sysadmin).
  • Design load balancing and content distribution system.
  • MySQL database administration.
  • C/C++/C# Programming
  • Ruby and Ruby on Rails Programming
  • Python and Django Programming
  • The WPF/C# on the .NET Framework Programming
  • The PHP/JAVA Programming
  • Machine Learning and Expert System.
  • Internet of Things.

The author's skills in the fields of electric and electronic:

  • The design of popular CPU / MCU systems.
  • Design FPGA / CPLD system (Xilinx - Altera).
  • Design and programming of DSP systems (Texas Instruments).
  • Embedded ARM system design.
  • The RTOS Programming
  • Design and programming electronic power systems.
  • PLC - inverter - sensor - electric control cabinet industrial.
  • Control systems distributed connection with Server.

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  • Curriculum
  • 1. Introduction
    • videocam
      The tasks to do in this course

      11m26s
    • videocam
      Overview of IC fabrication technology

      11m26s
    • videocam
      Introduction to FPGA

      11m26s
    • videocam
      Architecture of FPGA

      11m26s
  • 2. Hardware Design Language VHDL
    • videocam
      Introduction to VHDL language

      11m26s
    • videocam
      Data types of VHDL language

      11m26s
    • videocam
      Signals and Varialbes

      11m26s
    • videocam
      Logic type

      11m26s
    • videocam
      Syntax of VHDL Language

      11m26s
    • videocam
      Processes and Concurrent

      11m26s
    • videocam
      Subprograms and Packages

      11m26s
    • videocam
      Structure a VHDL design

      11m26s
    • videocam
      Test Bench in VHDL

      11m26s
    • videocam
      State Machine

      11m26s
    • videocam
      Implement an Entity

      11m26s
    • videocam
      Behavioral Model

      11m26s
    • videocam
      Event in VHDL

      11m26s
    • videocam
      Synthesize VHDL design

      11m26s
    • videocam
      Place and Route

      11m26s
  • 3. Design FPGA with Xilinx platform
    • videocam
      Product line of Xilinx

      11m26s
    • videocam
      The Vivado IDE

      11m26s
    • videocam
      I/O Pin Planning Tool

      11m26s
    • videocam
      IP Cores

      11m26s
    • videocam
      Design constraints

      11m26s
    • videocam
      Check and simulation

      11m26s
    • videocam
      Synthesize and download bitstream to FPGA

      11m26s
  • 4. Design FPGA with Altera platform
    • videocam
      Product line of Altera

      11m26s
    • videocam
      The Quartus Prime IDE

      11m26s
    • videocam
      Design constraints

      11m26s
    • videocam
      Check and simulation

      11m26s
    • videocam
      Synthesize and download bitstream to FPGA

      11m26s
  • 5. Design FPGA with MATLAB
    • videocam
      Introduction to HDL Coder

      11m26s
    • videocam
      Platforms are supported in MATLAB

      11m26s
    • videocam
      Design process in MATLAB

      11m26s
    • videocam
      Optimize HDL Code

      11m26s
    • videocam
      Check HDL Code

      11m26s
    • videocam
      Synthesize design VHDL

      11m26s
Logic
Design of FPGA Programmable Logic System


A field-programmable gate array - FPGA - is an integrated circuit designed to be configured by a customer or a designer after manufacturing – hence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC).

Circuit diagrams were previously used to specify the configuration, as they were for ASICs, but this is increasingly rare.

A Spartan FPGA from Xilinx

FPGAs contain an array of programmable logic blocks, and a hierarchy of reconfigurable interconnects that allow the blocks to be "wired together", like many logic gates that can be inter-wired in different configurations.

Logic blocks can be configured to perform complex combinational functions, or merely simple logic gates like AND and XOR. In most FPGAs, logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory.

Technical

Contemporary field-programmable gate arrays have large resources of logic gates and RAM blocks to implement complex digital computations. As FPGA designs employ very fast I/Os and bidirectional data buses, it becomes a challenge to verify correct timing of valid data within setup time and hold time.

Floor planning enables resource allocation within FPGAs to meet these time constraints. FPGAs can be used to implement any logical function that an ASIC could perform. The ability to update the functionality after shipping, partial re-configuration of a portion of the design and the low non-recurring engineering costs relative to an ASIC design, offer advantages for many applications.

Some FPGAs have analog features in addition to digital functions. The most common analog feature is programmable slew rate on each output pin, allowing the engineer to set low rates on lightly loaded pins that would otherwise ring or couple unacceptably, and to set higher rates on heavily loaded pins on high-speed channels that would otherwise run too slowly.

Also common are quartz-crystal oscillators, on-chip resistance-capacitance oscillators, and phase-locked loops with embedded voltage-controlled oscillators used for clock generation and management and for high-speed serializer-deserializer (SERDES) transmit clocks and receiver clock recovery.

Fairly common are differential comparators on input pins designed to be connected to differential signaling channels. A few "mixed signal FPGAs" have integrated peripheral analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) with analog signal conditioning blocks allowing them to operate as a system-on-a-chip.

Such devices blur the line between an FPGA, which carries digital ones and zeros on its internal programmable interconnect fabric, and field-programmable analog array (FPAA), which carries analog values on its internal programmable interconnect fabric.

Applications

An FPGA can be used to solve any problem which is computable. This is trivially proven by the fact FPGA can be used to implement a soft microprocessor, such as the Xilinx MicroBlaze or Altera Nios II. Their advantage lies in that they are sometimes significantly faster for some applications because of their parallel nature and optimality in terms of the number of gates used for a certain process.

FPGAs originally began as competitors to CPLDs to implement glue logic for PCBs. As their size, capabilities, and speed increased, they took over additional functions to the point where some are now marketed as full systems on chips (SoC).

Particularly with the introduction of dedicated multipliers into FPGA architectures in the late 1990s, applications which had traditionally been the sole reserve of DSPs began to incorporate FPGAs instead.

Another trend in the use of FPGAs is hardware acceleration, where one can use the FPGA to accelerate certain parts of an algorithm and share part of the computation between the FPGA and a generic processor.

Traditionally, FPGAs have been reserved for specific vertical applications where the volume of production is small. For these low-volume applications, the premium that companies pay in hardware costs per unit for a programmable chip is more affordable than the development resources spent on creating an ASIC for a low-volume application.

Today, new cost and performance dynamics have broadened the range of viable applications.

Design and Programming

To define the behavior of the FPGA, the user provides a design in a hardware description language (HDL) or as a schematic design. The HDL form is more suited to work with large structures because it's possible to just specify them numerically rather than having to draw every piece by hand.

However, schematic entry can allow for easier visualisation of a design. Then, using an electronic design automation tool, a technology-mapped netlist is generated. The netlist can then be fit to the actual FPGA architecture using a process called place-and-route, usually performed by the FPGA company's proprietary place-and-route software.

The user will validate the map, place and route results via timing analysis, simulation, and other verification methodologies. Once the design and validation process is complete, the binary file generated (also using the FPGA company's proprietary software) is used to (re)configure the FPGA.

This file is transferred to the FPGA/CPLD via a serial interface (JTAG) or to an external memory device like an EEPROM. The most common HDLs are VHDL and Verilog, although in an attempt to reduce the complexity of designing in HDLs, which have been compared to the equivalent of assembly languages, there are moves[by whom?] to raise the abstraction level through the introduction of alternative languages.

Table of Content

1. Introduction

  • The tasks to do in this course
  • Overview of IC fabrication technology
  • Introduction to FPGA
  • Architecture of FPGA

2. Hardware Design Language VHDL

  • Introduction to VHDL language
  • Data types of VHDL language
  • Signals and Varialbes
  • Logic type
  • Syntax of VHDL Language
  • Processes and Concurrent
  • Subprograms and Packages
  • Structure a VHDL design
  • Test Bench in VHDL
  • State Machine
  • Implement an Entity
  • Behavioral Model
  • Event in VHDL
  • Synthesize VHDL design
  • Place and Route

3. Design FPGA with Xilinx Platform

  • Product line of Xilinx
  • The Vivado IDE
  • I/O Pin Planning Tool
  • IP Cores
  • Design constraints
  • Check and simulation
  • Synthesize and download bitstream to FPGA

4. Design FPGA with Altera Platform

  • Product line of Altera
  • The Quartus Prime IDE
  • Design constraints
  • Check and simulation
  • Synthesize and download bitstream to FPGA

5. Design FPGA with MATLAB

  • Introduction to HDL Coder
  • Platforms are supported in MATLAB
  • Design process in MATLAB
  • Optimize HDL Code
  • Check HDL Code
  • Synthesize design VHDL